Research Article
Sobel Edge Detection using Parallel Architecture based on FPGA
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International Journal of Applied Information Systems
Foundation of Computer Science (FCS), NY, USA
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| Volume 3 - Issue 4 |
| Published: July 2012 |
| Authors: Varun Sanduja, Rajeev Patial |
10.5120/ijais12-450515
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Varun Sanduja, Rajeev Patial . Sobel Edge Detection using Parallel Architecture based on FPGA. International Journal of Applied Information Systems. 3, 4 (July 2012), 20-24. DOI=10.5120/ijais12-450515
@article{ 10.5120/ijais12-450515,
author = { Varun Sanduja,Rajeev Patial },
title = { Sobel Edge Detection using Parallel Architecture based on FPGA },
journal = { International Journal of Applied Information Systems },
year = { 2012 },
volume = { 3 },
number = { 4 },
pages = { 20-24 },
doi = { 10.5120/ijais12-450515 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2012
%A Varun Sanduja
%A Rajeev Patial
%T Sobel Edge Detection using Parallel Architecture based on FPGA%T
%J International Journal of Applied Information Systems
%V 3
%N 4
%P 20-24
%R 10.5120/ijais12-450515
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper proposes an FPGA based approach known as Sobel Edge Detection. RGB image is taken by the computer source and converted into binary image using MATLAB. The proposed Sobel Edge Detection is modeled using Parallel Architecture and implemented in Verilog HDL. The whole process is performed in the hardware level that utilizes the resources of Xilinx ISE 12. 4. The result shows good performance of edge detection with maximum frequency of 200 MHz. The time from image read to final edge determined image would vary with the image size. Also, the device utilization summary shows good results.
References
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